This application claims the priority benefit of Taiwan application Ser. No. 89120661, filed on Oct. 4, 2000.
1. Field of the Invention
The present invention relates to a thermal enhanced ball grid array package. More specifically, the present invention relates to a thermal enhanced ball grid array package having thermal balls.
2. Description of the Related Art
In the ever-expanding world of information, the integrated circuit is an inseparable part of daily life. Food, clothing, residence, business, education, and amusement are just some of the areas which often use products made with integrated circuits. Following constant development, greater user-friendliness, increased usefulness and higher complexity in electronic products, as well as a trend towards lightness and smallness in design, the use of electronic products has become more convenient and comfortable. In the semiconductor fabricating process, a semiconductor product having higher integration is available because of mass production of the 0.18 micron integrated circuit. However, the amount of heat generated from the device per area increases as the integration of the semiconductor device increases. Therefore, improvement of heat dissipation for the semiconductor package is important an affects the performance of the product greatly.
Referring to FIG. 1, a schematic, cross sectional view of a conventional matrix ball grid array package having thermal vias is shown.
As shown in FIG. 1, U.S. Pat. No. 5,894,410 discloses a central-and-periphery matrix ball grid array. The substrate 102 has a first surface 101 and a second surface 103 opposite to the first surface 101. The substrate 102 includes a plurality of patterned trace layers 108 and insulating layers 110 which are under the die pad 106 of the first surface 101. The patterned trace layers 108 are electrically connected to each other by plugs (not shown). The chip 120 is attached on the die pad 106 of the substrate 102 by a wire bond package technology, and is electrically connected to the gold fingers on the substrate 102 by wires 128. The chip 120 and the first surface 101 are encapsulated with a molding compound 122. Solder balls 124 are provided in a matrix on the ball pads 116 as external electrical connections. The through holes 114 penetrate the patterned trace layers 108 and the insulating layers 110 in the substrate to thermally connect the solder balls 124 to the chip 120.
The through holes 114 are designed to be provided under the chip 120, vertically penetrating the substrate 102. The length of the through hole 114 is substantially the same as the shortest distance from the first surface 101 to the second surface 103. However, the through hole 114 generally has a tubular profile, and the filling material therefor has considerable heat resistance so that the heat generated from the chip 120 can not be effectively dissipated off. Moreover, the heat generated from the chip 120 is transmitted to the solder balls 124 through the die pad 106 and the filling material in the through holes 114 and then ball pads 116. This makes the heat-dissipating path for the chip 120 longer and thus reduces the heat-dissipating performance.
Therefore, it is an object of the present invention to provide a thermal enhanced ball grid array package, which can be used in a semiconductor package. The chip can be attached on the metal core layer to transfer the heat generated from the chip to the metal core layer.
It is another object of the present invention to provide a thermal enhanced ball grid array package. In the package, a plurality of blind vias are formed between the metal core layer and the solder balls by laser ablating. A heat conductive material or a tin lead alloy is filled into the blind vias to form thermal balls.
It is still another object of the present invention to provide a heat-dissipating device for a semiconductor package. The heat from the chip to the metal core layer is transferred directly through the thermal balls. This provides the chip with an extremely short path for heat dissipation and increases the heat-dissipating rate and performance of a package.
According to the above and other objects of the present invention, a thermal enhanced ball grid array package is provided, comprising: a substrate, a chip, a molding compound, a plurality of solder balls, and a plurality of thermal balls. The substrate includes a metal core layer having a first surface and a second surface, with the first surface having a die pad region. At least a first patterned trace layer is provided in a region adjacent to the die pad region on the first surface. A first insulating layer is provided between the first patterned trace layer and the metal core layer. At least a second patterned trace layer is provided on the second surface. A second insulating layer between the second patterned trace layer and the metal core layer. The second patterned trace layer is electrically connected to the first patterned trace layer. The second patterned trace layer has a plurality of ball pads. A plurality of blind vias are provided in the second patterned trace layer and the second insulating layer to expose the second surface. A chip is provided in the die pad region and is electrically connected to the first patterned trace layer. A molding compound encapsulates the chip and part of the connection between the chip and the first patterned trace layer. A plurality of solder balls are provided on the surfaces of the ball pads. A plurality of thermal balls are provided in the blind vias and thermally connected to the second surface.
According to one preferred example of the present invention, the chip is attached directly on the metal core layer, so that the heat generated from chip can be directly transferred to the metal core layer. A plurality of blind vias are formed between the metal core layer and the solder balls by laser ablating. A heat conductive material and/or tin lead alloy is filled into the blind vias to form thermal balls, thereby dissipating the heat from the chip to the metal core layer through the thermal balls. This provides the chip with an extremely short path for heat dissipation. A heat sink can be additionally provided on the surface of the package to further increase the heat-dissipating rate and performance of a package.